?Q3? Answer the following questions relating to computer memory systems.
(1) Consider a full-associative cache memory implemented in a microprocessor chip.
Assume that the word size is 4 bytes, the cache size is 16 bytes, the block size is
4 bytes, and the address width is 4 bits. Block replacement policy is LRU (Least
Recently Used) algorithm. Suppose the cache is initially empty, and we have the
following sequence of memory references given as word addresses (represented in the
binary numeral system). Find the cache miss rate.
0101 \implies 1111 \implies 1001 \implies 0101 \implies 0001 \implies 1100 \implies 1111 \implies 0101 \implies 0011 \implies 1100
(2) It has been observed that 30% of total program execution time is consumed for
memory accesses. Here, we have optimized hardware design, and have made memory
accesses 3 times faster without causing any negative effects to performance. Calcu-
late the performance improvement ratio achieved by this hardware optimization.
