Suppose you are an engineer working at a chemical processing plant. You are required to
design a temperature detector system to monitor the temperature of three chemical tanks ($T_1$,
$T_2$ and $T_3$). Your system takes a 6-bit input representing the temperature, which has a range
from 0 to 64. If the measured temperature value of chemical tank is less than 46, set output
$T_1$ to 1. If the temperature value of chemical tank is 46 to 50, set output $T_2$ to 1. If the
temperature value of chemical tank is more than 50, set output $T_3$ to 1.
(a) Design in Verilog the proposed synchronous system with positive-edge triggered
clock. You are required to design the simple processor with the 3-bit outputs ($T_1$, $T_2$
and $T_3$), 6-bit input (sensor [5:0]), clock (CLK) and reset (RST) signals.
[10 marks]
