Texts: 2022_D...
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2022DD_m..
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fundamentals-..
2021_DD_fi.
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module FSM (input logic clk, reset; input logic [l:0] A; output logic y);
logic [l:0] state, nextstate;
parameter So =1'b0; parameter Sl=l'b1;
always_ff @ (posedge clk, posedge reset) if (reset) state <= S0; else state <= nextstate;
// state register
always_comb //next state logic case (state) S0: if(A==2'b00 | A==2'b11) nextstate=S0; else nextstate = Sl; S1: if (A==2'b01 |A==2'b10) nextstate=S0; else nextstate = Sl;
endcase
assign y=state== Sl;
// output logic
endmodule
(1) Draw its state transition diagram.
0,1I
010
O1,10
2 Show its truth table f for the next state logic (state transition table neft Stode elf pet. 'e=-
-oo-
o.-
(3 Derive its output logic and next-state logic functions. Minimize them if needed.
ABC
QI aV+y+23sn<= 6 i
(4 Draw its logic diagram using gates and flip-flops.
