Complete the behavioral VHDL code of a 4-bit up-counter that counts from 3 to 15. The counter has an asynchronous Resetn input that resets the counter back to 3 when Resetn = 0. The counter will count up if and only if it has a falling edge on its clock and its enable input E is equal to 1.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY upcount IS
PORT ( Clock, Resetn, E : IN STD_LOGIC);
END upcount;
ARCHITECTURE Behavior OF upcount IS
SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (Clock, Resetn)
BEGIN
IF Resetn = '0' THEN
Count <= "0011";
ELSIF (Clock'EVENT AND Clock = '0') THEN
IF E = '1' THEN
Count <= Count + 1;
END IF;
END IF;
END PROCESS;
END Behavior;
