We are using the S-siage pipeline described in section 4.5. We will use the following three instructions: or rl, r2, r3 or r2, rl, r4 or ri, rl, r2.
Here are the cycle times related to forwarding:
Without Forwarding:
ALU-ALU: 200 ps
With Forwarding:
ALU-ALU: 280 ps
With Full Forwarding:
ALU-ALU: 260 ps
Where are the data dependencies and what type are they?
In the table below, use one row per dependency you find. For each, do three things:
- Mark which register has the dependency
- Mark which instructions are involved in the dependency (always 2 or 3)
- Mark which of the three types of dependency it is: Read after Write (most common), Write after Write, or Write after Read
There is at least one of each type of hazard. You may not need all the rows.
R1 R2 R3 R4
1 1 2 1 1 2 1 3
R A W W A R W A W
b. If there is no forwarding at all, you will have hazards (the requirement to insert NOPs to address the data dependencies). Insert new rows with the instruction nop as needed to the code to avoid all hazards created by the data dependencies. The code to modify is:
or ri, r2, r3
nop
or r2, rl, r4
nop
or rl, rl, r2
If there is full forwarding (both from ALU to ALU and from MEM to ALU), what would the code look like?
or ri, r2, r3
or r2, rl, r4
or rl, rl, r2
d. In a 5-stage pipeline, we are executing a block of many lines of code that runs without delay (no stalls). How many cycles does it take to complete an instruction? What about each instruction after that? How long then do three instructions require?
Title_with_topic:
Analysis of Data Dependencies and Hazards in the S-siage Pipeline
