1. Stress test a combinational circuit
Given the function: $F(A, B, C) = \Sigma m(1, 3, 4, 6)$ having don't-care values: $d(A, B, C) = \Sigma m(7)$
(a) Model in Verilog the implementation of $F$ that would arise from it's canonical minterm form expression. Let's adopt the following propagation delays as a class-wide policy, so that our results become comparable:
• NOT: #5
• AND, OR: #10
• NAND, NOR: #12
• XOR, XNOR: #15
• Buf (buffer): #4
Please use the following directive at the top of all of your Verilog files: `timescale 1ns / 1ps`
This means: 1 time unit is 1 nanosecond and the simulation precision is 1 picosecond. So, #12 should simulate 12 nanoseconds of delay.
(b) Test that this circuit behaves correctly using a testbed that sends the following 10 inputs $X_i$ to it and visually verifying using terminal print statements and a waveform output:
$X = (010, 111, 001, 100, 011, 000, 110, 101, 011, 010)$
(c) Determine empirically the shortest inter-arrival time of inputs that this circuit could support while still performing correctly. You'll do this by modifying the delays in the testbed between when inputs change.
(d) Model in Verilog the implementation of $F$ that would arise from it's form after minimization. Adopt the same propagation delays and timescale directive as above.
(e) Test that it behaves correctly using the same testbed as above.
(f) Determine empirically the shortest inter-arrival time of inputs that this circuit could support while still performing correctly, using the same methodology as above.
