5) The enable input of a D-type latch is used to
a. control the tri-stateable Q output
b. control when the Q output equals the D input
c. prevent metastability
d. initialize the Q output to logic '0'
6) A counter has the count sequence 0, 5, 9, 122, 14, 0, 5, 9,... How many
registers does this counter require?
a. 6
b. 7
c. 8
d. 122
7) The outputs of a ring counter have a 50% duty cycle.
a. TRUE
b. FALSE
8) Which of the following is the count sequence of a modulo-5 counter?
a. 0, 1, 2, 3, 4, 0, 1, ...
b. 0, 1, 2, 3, 4, 5, 0, ...
9) You are using a 54HC160 counter as a modulo-7 counter. What is the output of
the counter when the clear input is asserted?
a. 8
b. 7
c. 6
d. 5