6. Consider the following program executing on a simple 5-stage MIPS pipeline
with forwarding for D and I-type instructions and single-cycle delayed loads.
The implementation employs a branch target buffer for branch prediction, with
misprediction resolution in MEM.
1000: start: add r2, r0, r0
1004: add r16, r0, r0
1008: add r17, r0, 400
1012: loop: lw r1, 0(r2)
1016: addi r16, r16, 4
1020: add r2, r2, r3
1024: bne r16, r17, loop
1028: jr r31
Assuming we start counting clock cycles at 1 with the fetch of the instruction
at address 1000, at the end of which clock cycle does the instruction at address
1028 successfully complete?
A. Cycle 1600.
B. Cycle 1614.
C. Cycle 16.
D. Cycle 1613.
