Assume a processor has 3 levels of caches. Suppose that the time required to access the L1 (primary) cache on a hit is 1 cycle, the local L1 cache hit ratio is 0.90, the time to access the L2 (secondary) cache on a hit is 5 cycles, the local L2 cache miss ratio is 0.25, the time to access the L3 cache on a hit is 10 cycles, the local L3 cache hit ratio is 0.50, and the L3 cache miss penalty to access main memory is 100 cycles. Give the average memory access time. Also give the average memory access time if this processor did not have an L2 and L3 cache.
