Moore Q3 You are asked to design a counter with a single...

Moore Q3 You are asked to design a counter with a single wire input M and a single wire output Y. When M = 1 the counter should operate modulo-5, and when M = 0 the counter should operate modulo-7. The output should be 1 only when the counter is at internal state zero. (a) Write down a state transition graph for your design. [8] (b) Complete the following state transition and output table, based on your transition graph design [4] S Input M 0 1 S0: 000 S1: 001 S2: 011 S3: 110 S4: 101 S5: 010 S6: 100 S7: 111 Q2Q1Q0 Q2*Q1*Q0*, Y Table Q3-1 (c) Derive the excitation logic equations for your design, assuming D-type flip-flops. [6] (d) Derive logic to drive the output Y. [2] (e) When various student designs for this counter are tested, a number of them briefly fail to act as modulo-5 or modulo-7 counters after changes of M. i) Give reasons why this might be the case, and indicate whether your design is subject to this problem. [3] ii) How might the problem be eased? [2]

Transcript

00:01 Okay, so the question here is, if i could just look at it again, is asking us to, we have a, we're to design a counter with a single wire input, m and a single wire output.

00:24 When m equals to 1, the counter should operate modular 5, and when m equals to 0, the counter should operate modular 7.

00:36 The output should be one, only when the counter is at internal state zero.

00:42 So the task here is for us to essentially write down a state transition graph for your design.

00:54 That's the one thing.

00:55 The other thing is to state whether it's a more machine or a mealy machine.

01:03 Okay, so that's pretty much what we're supposed to do here.

01:09 So first, let's answer that question about why, what type of machine in this is.

01:16 This is going to be a more machine.

01:19 And we can talk about that why it is a more machine.

01:27 So in fsm theory, there are two primary types of machines, which are more and mealy, right? in this problem, the output y is one only when the counter is in state as for other states, y equals zero.

01:46 So the output y does not depend on the input m, only on which state the machine is in, therefore it is a more machine.

01:59 Okay, so that's really what is happening here.

02:05 Now let's work out the problem here.

02:08 So again, this is a fsm, finance state machine.

02:15 And if you, well, let's just go ahead here.

02:19 We are designing a synchronous counter and we want to, i just want to give you some things here.

02:29 I have had some of this type, so i paste this in here.

02:35 So first of all, we would have the, we would have the, you would have the single single input, which is the m, the mode selector.

02:45 Think about this, right? you also have the single output.

02:51 It's y equals the 1, only when the counter is in state as 0.

02:56 Again, why i said this is a more machine.

02:59 So you have the two modes, you have the modula 5, which counts 0, 1, 2, 3, 4, 0, and module of 7, which counts 0, 2, 3, 4, 5, 6, and then go to 0.

03:11 Okay, so what we're going to do is to define all required states, and we're going to specify transitions for each value of m, and we're going to indicate the output logic, provide a state transition table, present that state transition graph.

03:32 And so what we need is seven total states, so s -0 through s -6.

03:43 So those are the states that we will need.

03:45 Right and these states are shared between the modes i'm just going to put this this down i'm going to put this i'm going to put this down here just go ahead and write this down here so so these states when it is seven total states i just said okay so in the transition behavior you want to see that when modular of zero so let me just write it down here when m equals to 0, when m equals to 0, that's modular 7, right? so, modged 7.

04:28 I see why i wanted to type because my handwriting is also.

04:33 So we would have the normal counting, right, as we talked about earlier.

04:40 So for m7, we have the normal counting.

04:46 So we're going to have here s0 all the way through s6 and then back to s0, right? and then if the, and then this is for m equals to zero.

05:01 Now let's go to m equals to 1.

05:04 So now when m equals to 1, that's going to be the mod 5.

05:10 Again, we've talked about this before, right? right over there, what would happen is that we would have the normal counting, right, which is s0 through s4, and then s0 again.

05:28 Okay, so we're going to have this going on, the normal counting.

05:33 Yeah, we just do this right here.

05:36 We're going to have that normal counting again.

05:41 But the thing here is that if the counter is an s5 or s6, it's going to reset to s0 to avoid the invalid state.

05:51 So let's talk about now the output logic.

05:54 So the output logic basically would be that y equals to 1 only in state 0, s0, and y will be equal to 0 in all other states.

06:06 Very simple...

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