Design a FSM that detects the pattern 101101 for an input binary sequence such as 1011010110... Its output is zero except when the consecutive 6 bits are 101101. In the example below, the output observed after each input bit is received is shown directly below the input bit received:
Input: 01101101111001
Output: 00000001000000
a) Draw the state transition diagram.
b) Determine the number of states required for this FSM.
c) Assign binary codes to each state.
d) Write the Verilog code for this FSM.