1. Objective: You will design and demonstrate a counter circuit using Verilog in this experiment. The counter takes in two 1-bit inputs, upDown and countSpeed, that control whether to count up or down and the increment value. If upDown is 1, it counts up and otherwise, counts down. If countSpeed is 0, it increments by 1; otherwise, it increments by 2. The design outputs seven segment driver values seg(a, b, c, d, e, f, g, dp).
2. Programs and Files Required: XinSE 14.7 cupDownCounter7seg.v (Verilog module to be completed), constraints.ucf (used in the implementation step).
3. Procedure Task 1: Complete the code by selecting a value for x so that the number increments roughly once every second. Complete the missing parts of the code so that the counter changes value based on the switch named upDown. The value of x controls the frequency at which the value of the seven-segment display changes. The value should change in roughly 1-second intervals. The Basys2 FPGA has a frequency of 50MHz, and x controls the speed that the number displayed by the seven-segment display will change. For example, x=0 will cause the LED to change values in every clock cycle (50 million times per second) and x=1 will change it 25 million times per second. Thus, the seven-segment will change values 50000/2 times per second.
Task 2: Add an input named countSpeed which controls how the circuit increments. You should add it to the port list, declare it as an input, map it to a physical switch on the FPGA, and then modify your code so the counter increments according to countSpeed.
4. Design behavior:
- upDown=1 and countSpeed=0: 1->2->3
- upDown=1 and countSpeed=1: 0->2->4->6
- upDown=0 and countSpeed=0: 5->4->3->2
- upDown=0 and countSpeed=1: 5->3->1->F
Sequential Part: driver circuit