Question

1. What is the size of the main memory for cache system B? Some portion of cache system B represented a 2-way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes). The tag and set number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag Set Number Word within block 00 01 10 11 10 1000 0100 1001 0110 1101 2016 6116 C116 2116 11 1100 0100 1001 0110 1101 3216 7216 C216 D216 10 1000 0100 1001 0110 1110 4216 8216 4116 A216 11 1100 0100 1101 0110 1110 5216 9216 8216 B216 10 1000 0100 1001 0110 1111 2016 6116 D116 5116 11 11000100 1001 0110 1111 3216 7216 C216 D216 10 1000 0100 1001 0111 0000 4216 8216 6116 1216 11 1100 0100 1101 0111 0000 5216 A216 5216 B216 10 1000 0100 1001 0111 0001 2716 6116 C116 2116 11 1100 0100 1001 0111 0001 3216 7216 C216 D26 10 1000 0100 1001 0111 0010 A216 8216 4116 A216 11110001001101 0111 0010 5216 9216 5216 B216 1. What is the size of the main memory for cache system B? 2. What is the size of cache memory? 3. If we request memory read from memory address F1 35 C3, what data do we read? 4. If we request memory read from memory address A1 25 BA, what data do we read? 5. If we access memory in the following order in cache system B: A1 FF B8 81FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 how many cache miss(es) would occur for the data request?

          1. What is the size of the main memory for cache system B?
Some portion of cache system B represented a 2-way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes). The tag and set number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal.
Tag
Set Number
Word within block
00
01
10
11
10 1000 0100 1001
0110 1101
2016
6116 C116
2116
11 1100 0100 1001
0110 1101
3216
7216
C216
D216
10 1000 0100 1001
0110 1110
4216
8216 4116 A216
11 1100 0100 1101
0110 1110
5216
9216 8216
B216
10 1000 0100 1001
0110 1111
2016
6116
D116
5116
11 11000100 1001
0110 1111
3216
7216
C216
D216
10 1000 0100 1001
0111 0000
4216
8216
6116
1216
11 1100 0100 1101
0111 0000
5216
A216
5216
B216
10 1000 0100 1001
0111 0001
2716
6116 C116 2116
11 1100 0100 1001
0111 0001
3216
7216
C216
D26
10 1000 0100 1001
0111 0010
A216
8216
4116
A216
11110001001101
0111 0010
5216
9216
5216
B216
1. What is the size of the main memory for cache system B?
2. What is the size of cache memory?
3. If we request memory read from memory address F1 35 C3, what data do we read?
4. If we request memory read from memory address A1 25 BA, what data do we read?
5. If we access memory in the following order in cache system B:
A1 FF B8
81FF B8 A1 FF B8
B1 FF B8
A1 FF B8
B1 FF B8
how many cache miss(es) would occur for the data request?

1 what is the size of the main memory for cache system b some portion of cache system b represented a 2 way set associative mapping cache system the system is byte addressable and the block 08618

Added by Rafael W.

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