Question

1. Write a behavioral VHDL module that implements the 8-bit shift register of Figure A. SI (Serial in) 8-Bit Serial-In, Serial-Out Shift Register SO (Serial out) (Serial in) ? CLK (a) Block diagram (Serial out) ---00000000- CLK (b) Logic diagram Figure A. Do not use individual flip-flops in your code. Add an active-low asynchronous reset input, ClrN. Simulate the module to obtain a timing diagram similar to Figure B. Then, write VHDL code for a 16-bit serial-in, serial-out shift register using two of these modules. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK SI 7 Clock Periods SO -7 Clock Periods- Figure B.

          1. Write a behavioral VHDL module that implements the 8-bit shift register of Figure A.
SI
(Serial in)
8-Bit Serial-In, Serial-Out
Shift Register
SO
(Serial out)
(Serial in)
?
CLK
(a) Block diagram
(Serial out)
---00000000-
CLK
(b) Logic diagram
Figure A.
Do not use individual flip-flops in your code. Add an active-low asynchronous reset input, ClrN.
Simulate the module to obtain a timing diagram similar to Figure B. Then, write VHDL code for
a 16-bit serial-in, serial-out shift register using two of these modules.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
SI
7 Clock Periods
SO
-7 Clock Periods-
Figure B.

1. Write a behavioral VHDL module that implements the 8-bit shift register of Figure A.
SI
(Serial in)
8-Bit Serial-In, Serial-Out
Shift Register
SO
(Serial out)
(Serial in)
?
CLK
(a) Block diagram
(Serial out)
—00000000-
CLK
(b) Logic diagram
Figure A.
Do not use individual flip-flops in your code. Add an active-low asynchronous reset input, ClrN.
Simulate the module to obtain a timing diagram similar to Figure B. Then, write VHDL code for
a 16-bit serial-in, serial-out shift register using two of these modules.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
SI
7 Clock Periods
SO
-7 Clock Periods-
Figure B.

Added by Juan Manuel M.

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