Problem 3. (16 pts) Assume that you have the following VHDL code of a 2:1 multiplexer mux2. library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux2 is port(d0, d1, s: in STD_LOGIC; y: out STD_LOGIC); end; architecture synth of mux2 is begin y <= d1 when s = '1' else d0; end; Write down VHDL code to describe the circuit shown in the following schematic by using structure modeling with the mux2 given above. The circuit has the following one-bit input ports: A, B, C, D, E, F, and a clock signal clock. The circuit has two one-bit output ports: Y1 and Y0. Note that your VHDL code should use the names of the signals (including all input, output, and internal signals) given in the following schematic.
Added by Timothy M.
Close
Step 1
** The circuit consists of: * **Six input ports:** A, B, C, D, E, and F. * **One clock input:** clock. * **Two output ports:** Y1 and Yo. * **Four D flip-flops:** P1, P2, P3, and P4. * **Logic gates:** AND gates, OR gates. Show more…
Show all steps
Your feedback will help us improve your experience
Sri K and 64 other Calculus 3 educators are ready to help you.
Ask a new question
Labs
Want to see this concept in action?
Explore this concept interactively to see how it behaves as you change inputs.
Key Concepts
Recommended Videos
In the following VHDL process A, B, C, and D are all integers that have a value of 0 at time = 10 ns. If E changes from '0' to '1' at time 20 ns, specify the time at which each signal will change and the value to which it will change. p1: process wait on E; A <= 1 after 15 ns; B <= A + 1; C <= B + 1 after 10 ns; D <= B + 2 after 3 ns; A <= A + 5 after 15 ns; B <= B + 7; end process p1;
Adi S.
The below sequential circuit is built using JK flip-flops. It is initialized with the initial values of A=1, B=0, and external input x is set to 0. What are the next state values of A and B for this circuit for the next clock cycle? Clk KA TB Clk Clock Select one: A(t+1)=1, B(t+1)=0 A(t+1)=x, B(t+1)=0 A(t+1)=1, B(t+1)=1 A(t+1)=0, B(t+1)=1 A(t+1)=0, B(t+1)=0 A(t+1)=1, B(t+1)=x
Manish J.
Question 1: We wish to build a 3-bit synchronous counter using edge-triggered J-K flip-flops with outputs Q3, Q2, and Q1. A schematic diagram (minus the logic for the flip-flop inputs) is shown below: The counter must output the following sequence of decimal numbers in 3-bit binary: 2 → 4 → 7 → 5 → 2 → .... The output of the counter is Q3Q2Q1. Assume that the counter never starts or gets into an illegal state. (a) Write down the state diagram for this counter. (b) Write down the next state table for this counter. (c) Write down the flip-flop transition table for a J-K flip-flop.
Maitreya E.
Recommended Textbooks
Calculus: Early Transcendentals
Thomas Calculus
Transcript
Watch the video solution with this free unlock.
EMAIL
PASSWORD
