123. Explain the concept of Very Long Instruction Word (VLIW) architecture in microprocessors.
Added by Spencer V.
Step 1
It is a type of microprocessor architecture where a single instruction word contains multiple instructions that can be executed in parallel. Show more…
Show all steps
Your feedback will help us improve your experience
Akash M and 80 other Physics 102 Electricity and Magnetism educators are ready to help you.
Ask a new question
Labs
Want to see this concept in action?
Explore this concept interactively to see how it behaves as you change inputs.
Key Concepts
Recommended Videos
Consider the description of the VAX architecture in Section 1.4.1. What characteristics would you expect to find in a VAX assembler?
Assemblers
Implementation Examples
Explain the architecture of ARM processor.
Roee S.
Amdahl's law states that if you speed up portions of a program eventually the parts you do not parallelize (that are sequential) will dominate the running time, and thus you reach the point of diminishing returns. This can be represented, in its most general form, with the formula: S_latency(s) = 1 / ((1 - p) + (p / s)) where: S_latency is the theoretical speedup of the execution of the whole task; s is the speedup of the part of the task that benefits from improved system resources; p is the proportion of execution time that the part benefiting from improved resources originally occupied. For programs with multiple parts that can be parallelized, the following formula will apply: S_latency = 1 / ((p1 / s1) + (p2 / s2) + (p3 / s3) + (p4 / s4)) You will need to modify these formulas to account for the additional parallelization provided by VLIW. For this problem, consider a program in which the dynamic execution breakdown of operations (assume unit latency) is the following: 14% memory ops 45% integer ALU ops 30% branches 11% floating-point ops Answer the following questions: 1. What is the speed-up of the above program for a 4-wide VLIW machine with one memory unit, one integer unit, one branch unit, and one floating-point unit? 2. What is the speed-up of the above program for an 8-wide VLIW machine with two memory units, two integer units, three floating-point units, and one branch unit? 3. What is the speed-up of the above program for a VLIW machine (with infinite width) with one integer unit and unlimited other functional units? Calculate speed-up for each of the above questions compared to sequential execution and assume no data dependencies.
Akash M.
Recommended Textbooks
University Physics with Modern Physics
Physics: Principles with Applications
Fundamentals of Physics
Transcript
18,000,000+
Students on Numerade
Trusted by students at 8,000+ universities
Watch the video solution with this free unlock.
EMAIL
PASSWORD