12. Inverter propagation delay: time delay between input and output signals; figure of merit of logic speed. Assume the figure below shows the input to an inverter, complete the figure by showing/labeling tpHL, tpLH, tf, tr.
13. Consider the CMOS inverter pictured below. Take channel length modulation into account.
VDD = 1.5V
W/L = 12/1.5
Vin
Vout
Cload = 0.5pF
W/L = 6/1.5
Dimensions of W and L are in μm.
a) Calculate VM, the voltage midpoint.
b) Calculate AV, the voltage gain at Vin = VM.
c) Calculate NML and NMH, the noise margin low and noise margin high.
d) Calculate tPHL and tPLH, the propagation delay from high-to-low and propagation delay from low-to-high.