Question

1. Write an RTL Verilog code that can convert any input rising edge to a five-clock period pulse Input Clock Output Hint: use a counter In your homework, attach both the RTL and Testbench code, and simulation result. 2. Write an RTL Verilog code for a PISO (parallel input serial output). The input is 8-bit, and the output is 1-bit. The output clock is 8 times faster than the input clock. The circuit is triggered by posedge clk and reset, a load signal is used to write the input data into the circuit. Hint: use an 8-bit shift register In your homework, attach both the RTL and Testbench code, and simulation result.

          1. Write an RTL Verilog code that can convert any input rising edge to a five-clock
period pulse
Input
Clock
Output
Hint: use a counter
In your homework, attach both the RTL and Testbench code, and simulation result.
2. Write an RTL Verilog code for a PISO (parallel input serial output). The input is
8-bit, and the output is 1-bit. The output clock is 8 times faster than the input clock.
The circuit is triggered by posedge clk and reset, a load signal is used to write the
input data into the circuit.
Hint: use an 8-bit shift register
In your homework, attach both the RTL and Testbench code, and simulation result.

1. Write an RTL Verilog code that can convert any input rising edge to a five-clock
period pulse
Input
Clock
Output
Hint: use a counter
In your homework, attach both the RTL and Testbench code, and simulation result.
2. Write an RTL Verilog code for a PISO (parallel input serial output). The input is
8-bit, and the output is 1-bit. The output clock is 8 times faster than the input clock.
The circuit is triggered by posedge clk and reset, a load signal is used to write the
input data into the circuit.
Hint: use an 8-bit shift register
In your homework, attach both the RTL and Testbench code, and simulation result.

Added by Elizabeth S.

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