Question

1. You have the following top level design with 4-bit inputs A and B, and single bit output F. The decoder block is described in the Verilog code below. Complete the timing diagram for this circuit. Write t2 and F in binary. module Decoder ( input [3:0] A, output logic [2:0] D ); always_comb begin case (A) 4'b0000 : D = 3'h7; 4'b0001 : D = 3'h2; 4'b0010 : D = 3'h1; 4'b0111 : D = 3'h6; 4'b1011 : D = 3'h3; default: D = 3'h0; endcase end endmodule 2. Design a circuit that performs as follows: If the sum of the circuit's two 10-bit binary inputs (A, B) generates a carry-out and input A is even, the circuit outputs the A input, otherwise the circuit outputs the 10-bit sum. Use only an RCA, mux, and gates in your design.

          1. You have the following top level design with 4-bit inputs A and B, and single bit output F. The decoder block is described in the Verilog code below. Complete the timing diagram for this circuit. Write t2 and F in binary.

module Decoder (
input [3:0] A,
output logic [2:0] D );
always_comb
begin
case (A)
4'b0000 : D = 3'h7;
4'b0001 : D = 3'h2;
4'b0010 : D = 3'h1;
4'b0111 : D = 3'h6;
4'b1011 : D = 3'h3;
default: D = 3'h0;
endcase
end
endmodule

2. Design a circuit that performs as follows: If the sum of the circuit's two 10-bit binary inputs (A, B) generates a carry-out and input A is even, the circuit outputs the A input, otherwise the circuit outputs the 10-bit sum. Use only an RCA, mux, and gates in your design.

1. You have the following top level design with 4-bit inputs A and B, and single bit output F. The decoder block is described in the Verilog code below. Complete the timing diagram for this circuit. Write t2 and F in binary.

module Decoder (
input [3:0] A,
output logic [2:0] D );
alwayscomb
begin
case (A)
4'b0000 : D = 3'h7;
4'b0001 : D = 3'h2;
4'b0010 : D = 3'h1;
4'b0111 : D = 3'h6;
4'b1011 : D = 3'h3;
default: D = 3'h0;
endcase
end
endmodule

2. Design a circuit that performs as follows: If the sum of the circuit's two 10-bit binary inputs (A, B) generates a carry-out and input A is even, the circuit outputs the A input, otherwise the circuit outputs the 10-bit sum. Use only an RCA, mux, and gates in your design.

Added by Crystal W.

Question

Please give Ace some feedback