2. Timing analysis
Assume that teq and tsu for flip-flops is 1 ns, and th is 0.5 ns; the delay through a logic gate is given by 1 + k * 0.1 ns, where k is the number of inputs to the gate. Consider the circuit below:
clock
(a) Assuming teq = tsu = 3 ns, th = 4 ns, what is the critical path in the circuit, and what is the minimum clock period for which this circuit will work properly?
(b) Repeat part (a) assuming teq = 0.8 ns, tsu = 2 ns, th = 0.5 ns, and t4 = 3.0 ns.
(c) Assuming teq = 0 ns, tsu = 1.8 ns, th = 3.0 ns, and t4 = 1.7 ns, identify all possible hold time violations.