mnsu.learn.minnstate.edu
Objective: This is an introductory lab to Verilog HDL. In this lab, we will learn how to create modules in Verilog and then simulate the module for functionality and timing.
Steps:
1. Start the tutorial from section 1.
2. Create a Verilog file.
3. Using the editor, create a module. (Use the circuit in the tutorial)
4. Compile the module and check the summary. (Skip section 5 on page 15 and move to section 6 on page 18)
5. Create a testbench file, write a testbench to test your module.
6. Simulate your design and verify functionality using a truth table.
Try yourself:
a. After you are done with the tutorial, check your understanding using the following code:
module fa_mix(A, B, CI, sum, co);
input A, B, CI;
output sum, co;
reg co;
reg T1, T2, T3;
wire S1;
xor X1(S1, A, B); // gate instantiation
always @(A or B or CI) // behavior style
begin
T1 = A & B;
T2 = A & CI;
T3 = B & CI;
co = (T1 | T2) | T3;
end
assign sum = S1 ^ CI; // continuous assignment
endmodule
This is a 1-bit adder circuit where A, B, CI are inputs and sum and co are the summation and the carry out for the next stage.
b. Generate the truth table for an adder circuit.