Question

3.4 Design a 4-bit counter using the LS163A (74x163) 4-bit binary counter shown in Figure 1 with state $Q_DQ_CQ_BQ_A$. Use each of the following counting sequences. Construct the state table, derive the excitation equations for CLR, LD, D, C, B, and A, and draw the logic circuit. Assume both ENP and ENT are connected to power (set to high level). Assume CLR has precedence over LD. Draw a clock signal into the CLK input and the connection to power for ENP and ENT. 74x163 2 CLK 1 CLR 9 LD 7 ENP 10 ENT 3 A 14 QA 4 B 13 QB 5 C 12 QC 6 D 11 QD 15 RCO Figure 1: LS163A 4-bit synchronous counter block diagram. a. Design for the counting sequence (shown in decimal numbers): 0 \rightarrow 1 \rightarrow 2 \rightarrow 3 \rightarrow 4 \rightarrow 6 \rightarrow 8 \rightarrow 9 \rightarrow 10 \rightarrow 12 \rightarrow 14 \rightarrow 15 \rightarrow 0 \rightarrow ... b. Design for the counting sequence (shown in decimal numbers): 0 \rightarrow 1 \rightarrow 2 \rightarrow 3 \rightarrow 11 \rightarrow 10 \rightarrow 9 \rightarrow 8 \rightarrow 0 \rightarrow ...

          3.4 Design a 4-bit counter using the LS163A (74x163) 4-bit binary counter shown in Figure 1 with state $Q_DQ_CQ_BQ_A$. Use each of the following counting sequences. Construct the state table, derive the excitation equations for CLR, LD, D, C, B, and A, and draw the logic circuit. Assume both ENP and ENT are connected to power (set to high level). Assume CLR has precedence over LD. Draw a clock signal into the CLK input and the connection to power for ENP and ENT.
74x163
2 CLK
1 CLR
9 LD
7 ENP
10 ENT
3 A
14 QA
4 B
13 QB
5 C
12 QC
6 D
11 QD
15 RCO
Figure 1: LS163A 4-bit synchronous counter block diagram.
a. Design for the counting sequence (shown in decimal numbers):
0 \rightarrow 1 \rightarrow 2 \rightarrow 3 \rightarrow 4 \rightarrow 6 \rightarrow 8 \rightarrow 9 \rightarrow 10 \rightarrow 12 \rightarrow 14 \rightarrow 15 \rightarrow 0 \rightarrow ...
b. Design for the counting sequence (shown in decimal numbers):
0 \rightarrow 1 \rightarrow 2 \rightarrow 3 \rightarrow 11 \rightarrow 10 \rightarrow 9 \rightarrow 8 \rightarrow 0 \rightarrow ...

3.4 Design a 4-bit counter using the LS163A (74x163) 4-bit binary counter shown in Figure 1 with state QDQCQBQA. Use each of the following counting sequences. Construct the state table, derive the excitation equations for CLR, LD, D, C, B, and A, and draw the logic circuit. Assume both ENP and ENT are connected to power (set to high level). Assume CLR has precedence over LD. Draw a clock signal into the CLK input and the connection to power for ENP and ENT.
74x163
2 CLK
1 CLR
9 LD
7 ENP
10 ENT
3 A
14 QA
4 B
13 QB
5 C
12 QC
6 D
11 QD
15 RCO
Figure 1: LS163A 4-bit synchronous counter block diagram.
a. Design for the counting sequence (shown in decimal numbers):
0 →1 →2 →3 →4 →6 →8 →9 →10 →12 →14 →15 →0 →...
b. Design for the counting sequence (shown in decimal numbers):
0 →1 →2 →3 →11 →10 →9 →8 →0 →...

Added by Andrew S.

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