4A. (35 points) Complete the following VHDL module:
entity X4 is
port(
CLK: in bit;
OCLR: in bit;
PS: out bit_vector(2 downto 0);
Z: out bit
);
end entity X4;
architecture logic of X4 is
signal ps, ns: bit_vector(2 downto 0);
begin
process(CLK, OCLR)
begin
if(OCLR = '0') then
ps <= "000";
elsif rising_edge(CLK) then
ps <= ns;
end if;
ns <= bit;
end process;
Z <= ps(0);
end architecture logic;
4B. (5 points) Which machine type is this?
Mealy, Moore, or Both? Check one: Both