Question

7. Now consider an E20 computer that has two caches: the L1 cache is an 8-row direct-mapped cache with a blocksize of 32 bits. the L2 cache is a 4-row 2-way set-associative cache with a blocksize of 64 bits. E20 memory addresses are 13 bits. Memory cells are 16 bits. The caches are initially empty. Instruction reads are not cached (in other words, only lw and sw affect the cache). Write an E20 assembly language program that will generate a memory reference that causes a miss on L1, but a hit on L2. In a comment in your program, specify the tag and index of the access in question. Your program should be as short as possible.

          7. Now consider an E20 computer that has two caches:  the L1 cache is an 8-row direct-mapped cache with a blocksize of 32 bits.  the L2 cache is a 4-row 2-way set-associative cache with a blocksize of 64 bits. E20 memory addresses are 13 bits. Memory cells are 16 bits. The caches are initially empty. Instruction reads are not cached (in other words, only lw and sw affect the cache). Write an E20 assembly language program that will generate a memory reference that causes a miss on L1, but a hit on L2. In a comment in your program, specify the tag and index of the access in question. Your program should be as short as possible.

Added by Dana W.

Question

Please give Ace some feedback