Question

3) Making the same assumptions as above, use a single '138 3-to-8 decoder and as few NAND gates as possible to design a memory circuit to fully decode the following address space: Unit size/type Start Address U1 2k Ram $6800 U2 2k RAM $F000 U3 2k RAM $7800 and to partially decode, via a 2-level scheme using an additional 1/2 of a '139 four 256 byte I/O devices having the following starting addresses: I/O 0 $6000 I/O 1 $6100 I/O 2 $6200 I/O 3 $6300

          3) Making the same assumptions as above, use a single '138 3-to-8 decoder
and as few NAND gates as possible to design a memory circuit to fully
decode the following address space:
Unit
size/type
Start Address
U1
2k Ram
$6800
U2
2k RAM
$F000
U3
2k RAM
$7800
and to partially decode, via a 2-level scheme using an additional 1/2 of
a '139 four 256 byte I/O devices having the following starting addresses:
I/O 0
$6000
I/O 1
$6100
I/O 2
$6200
I/O 3
$6300

3) Making the same assumptions as above, use a single '138 3-to-8 decoder
and as few NAND gates as possible to design a memory circuit to fully
decode the following address space:
Unit
size/type
Start Address
U1
2k Ram
6800
U2
2k RAMF000
U3
2k RAM
7800
and to partially decode, via a 2-level scheme using an additional 1/2 of
a '139 four 256 byte I/O devices having the following starting addresses:
I/O 06000
I/O 1
6100
I/O 26200
I/O 3
6300

Added by Rhonda V.

Computer Science and Information Technology

Trishna Knowledge Systems 2018 Edition

Instant Answer

Solved by Expert Akash M

Step 1

We have 16 address lines, so we need to fully decode 2^16 = 65536 addresses. The '138 3-to-8 decoder has three address inputs (A0, A1, A2) and eight outputs (Y0-Y7). We can use the three most significant address lines (A13, A14, A15) as inputs to the Show more…

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Assume a microcontroller with sixteen address lines - assume 16 address bits, A15 most significant. 3) Making the same assumptions as above, use a single '138 3-to-8 decoder and as few NAND gates as possible to design a memory circuit to fully decode the following address space: Unit size/type Start Address U1 U2 U3 2k RAM 2k RAM 2k RAM $6800 $F000 $7800 and to partially decode, via a 2-level scheme using an additional 1/2 of a 139 four 256 byte I/O devices having the following starting addresses: I/O $6000 I/O 1 $6100 I/O 2 $6200 I/O 3 $6300