Assume you have a 4-bit adder component (called "adder4") whose block diagram is shown in the simplified figure below. Generate a complete VHDL module called "adder8" that will use two 4-bit adders to create an 8-bit adder with carry out and carry in. Drawing a diagram of the complete system will make it easier to write the program.
Generate the complete architecture portion of a test-bench module for the 8-bit adder. You should test for the addition of the following input pairs:
10310 and 8810
25510 and 20010.
What values do you expect your output signals will take for the two cases above?
a
sum
4-bit
b
adder
Cout
Cin