Question

c. Assume MIPS is processing the following program: LW R1, 0(R2) SUB R4, R1, R5 AND R6, R1, R7 OR R8, R1, R9 Also assuming the forwarding mechanism is supported with MIPS. Does the MIPS pipeline need to be stalled during the execution of the above program? Explain by using a diagram similar to the one below. IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg Add R1, R2, R3 Sub R4, R1, R5 AND R6, R1, R7 OR R8, R1, R9 XOR R10, R1, R11

          c. Assume MIPS is processing the following program:
LW	R1, 0(R2)
SUB	R4, R1, R5
AND	R6, R1, R7
OR	R8, R1, R9
Also assuming the forwarding mechanism is supported with MIPS. Does the
MIPS pipeline need to be stalled during the execution of the above program?
Explain by using a diagram similar to the one below.
IM	Reg	ALU	DM	Reg
IM	Reg	ALU	DM	Reg
IM	Reg	ALU	DM	Reg
IM	Reg	ALU	DM	Reg
IM	Reg	ALU	DM	Reg
Add R1, R2, R3
Sub R4, R1, R5
AND R6, R1, R7
OR R8, R1, R9
XOR R10, R1, R11

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c. Assume MIPS is processing the following program:
LW R1, 0(R2)
SUB R4, R1, R5
AND R6, R1, R7
OR R8, R1, R9
Also assuming the forwarding mechanism is supported with MIPS. Does the
MIPS pipeline need to be stalled during the execution of the above program?
Explain by using a diagram similar to the one below.
IM Reg ALU DM Reg
IM Reg ALU DM Reg
IM Reg ALU DM Reg
IM Reg ALU DM Reg
IM Reg ALU DM Reg
Add R1, R2, R3
Sub R4, R1, R5
AND R6, R1, R7
OR R8, R1, R9
XOR R10, R1, R11

Added by Karina G.

Computer Science and Information Technology

Trishna Knowledge Systems 2018 Edition

Instant Answer

Solved by Expert Anecia Mcmurrin-Bala

Step 1

LW R1, 0(R2): This instruction loads the value from memory at the address stored in R2 and stores it in R1. Since this is a load instruction, it will take one cycle to fetch the instruction, one cycle to decode it, and one cycle to access memory and get the value. Show more…

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Assume MIPS is processing the following program: LW R1, 0(R2) SUB R4, R1, R5 AND R6, R1, R7 OR R8, R1, R9 Also assuming the forwarding mechanism is supported with MIPS. Does the MIPS pipeline need to be stalled during the execution of the above program? Explain by using a diagram similar to the one below. ALU Reg Add R1, R2, R3 Sub R4, R1, R5 AND R6, R1, R7 Reg OR R8, R1, R9 XOR R10, R1, R11

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