Question

1. a) Use Quartus to create a structural Verilog model of a 3x8 decoder using only NAND gates and inverters. You may use NAND gates having any number of inputs. Simulate the Verilog model, and verify that it gives the correct output. Carefully consider what set of input values would provide a good test of the multiplexer's function. Submit the source code for your Verilog model, and the simulation waveform that shows all inputs and outputs. b) Count the number of transistors in the circuit that you represented in part (a) of this problem. Show your calculations. c) Using the decoder module you created for part a, implement the Boolean function F(X,Y,Z) = XY'Z' + XY'Z' + XYZ by instantiating the decoder and one OR gate. Submit the source code for your Verilog model, and the simulation waveform that shows all inputs and outputs. Reminder: Put the decoder module definition in the same .v file as your top-level module. Make sure your .v file has the same name as your top-level module. The inputs to the top-level module should X, Y and Z; the output should be F. You will need to declare wires to connect the decoder and OR gate in your top-level module. Hint: If you need to concatenate signals in Verilog, use {........} For example, to combine the three scalar signals A, B, and C into a 3-bit vector with A as the most significant bit and C as the least significant bit, it looks like this {A,B,C}

          1.
a) Use Quartus to create a structural Verilog model of a 3x8 decoder using only NAND gates and inverters.
You may use NAND gates having any number of inputs. Simulate the Verilog model, and verify that it gives the
correct output. Carefully consider what set of input values would provide a good test of the multiplexer's
function.
Submit the source code for your Verilog model, and the simulation waveform that shows all inputs and outputs.
b) Count the number of transistors in the circuit that you represented in part (a) of this problem. Show your
calculations.
c) Using the decoder module you created for part a, implement the Boolean function
F(X,Y,Z) = XY'Z' + XY'Z' + XYZ
by instantiating the decoder and one OR gate. Submit the source code for your Verilog model, and the
simulation waveform that shows all inputs and outputs.
Reminder: Put the decoder module definition in the same .v file as your top-level module. Make sure your .v file has the
same name as your top-level module. The inputs to the top-level module should X, Y and Z; the output should be F. You
will need to declare wires to connect the decoder and OR gate in your top-level module.
Hint: If you need to concatenate signals in Verilog, use {........} For example, to combine the three scalar signals A, B,
and C into a 3-bit vector with A as the most significant bit and C as the least significant bit, it looks like this {A,B,C}

1.
a) Use Quartus to create a structural Verilog model of a 3x8 decoder using only NAND gates and inverters.
You may use NAND gates having any number of inputs. Simulate the Verilog model, and verify that it gives the
correct output. Carefully consider what set of input values would provide a good test of the multiplexer's
function.
Submit the source code for your Verilog model, and the simulation waveform that shows all inputs and outputs.
b) Count the number of transistors in the circuit that you represented in part (a) of this problem. Show your
calculations.
c) Using the decoder module you created for part a, implement the Boolean function
F(X,Y,Z) = XY'Z' + XY'Z' + XYZ
by instantiating the decoder and one OR gate. Submit the source code for your Verilog model, and the
simulation waveform that shows all inputs and outputs.
Reminder: Put the decoder module definition in the same .v file as your top-level module. Make sure your .v file has the
same name as your top-level module. The inputs to the top-level module should X, Y and Z; the output should be F. You
will need to declare wires to connect the decoder and OR gate in your top-level module.
Hint: If you need to concatenate signals in Verilog, use ........ For example, to combine the three scalar signals A, B,
and C into a 3-bit vector with A as the most significant bit and C as the least significant bit, it looks like this A,B,C

Added by Wayne R.

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