Consider a hypothetical machine with 1K words of cache memory. They are in a direct-mapped organization with a cache block size of 128 words, using the LRU replacement algorithm. Suppose the cache hit time is 10ns, the time to transfer the first word from main memory to cache is 9ns, while subsequent words require 12ns/word. Consider the following read pattern (in blocks of 128 words, and block id starts from 0): 123562349101163617845911124512131415 13 14 and assume each block contains an average of 48 references.
(a) What is the cache miss penalty (i.e., time to transfer one block of data from main memory to cache memory)?
(b) Write down the content of the cache memory (for all the blocks) at the end of the memory references, assuming that the cache is empty at the beginning.
(c) Write down the number of cache misses (the first reading of a block is also considered a miss), and the cache hit rate.
(d) Calculate the average memory access time.