Construct a synchronous sequence circuit with three inputs, a, b, and reset, except clock. The values of the two inputs, a and b, are changed simultaneously (synchronously). The circuit has an output, u, which is activated if ab=00 twice in succession. If this happens, a is given on the output u. The reset must remain activated until the reset is activated (reset=1). The reset signal must be in sync.
Example: a: 01011101011100010101 b: 10111101010110001010 : 00000000000000111111
Present the VHDL code with (entity and architecture)