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Figure 0. shows the datapath and control unit of a single-cycle RISC-V microprocessor. PCSrc Lnit MernWrite ALUCOUb 1418 TunclS ALL>re nS Zer6 RogVrita CLK CLK A WC3 D RD Instruction Memory WE ALURo A2 4X g Reg/etor File RD Cate Memory GM WriteData Extend Zero Branch Jump - PCSrc ResultSrc MornWrite ALUSrc ImmSrc RegWrite Main Decoder open ALUOP+% funct320 funct7g ALU Decoder ALUControl Figure 0. Single-cycle RISC-V datapath and control unit For the instruction beq sl, s2, Label, which of the datapath elements are active and why? In addition, to execute this instruction, what should be the outputs of the control unit? Specify the outputs of the control unit in Table 0 using 0, 1 and X (don't care) signals and for the ALU Unit, the type of operation, e.g. addition, subtraction, etc. Table 0. Control Unit signals Signal name PCSrc ResultSrc MemWrite ALUControl ALUSrc ImmSrc RegWrite ALUOp Branch Jump Zero ImmExt Value Explain Why

          Figure 0. shows the datapath and control unit of a single-cycle RISC-V microprocessor.
PCSrc
Lnit MernWrite ALUCOUb 1418 TunclS ALL>re nS Zer6 RogVrita
CLK
CLK A WC3 D
RD Instruction Memory
WE
ALURo
A2 4X g Reg/etor File
RD Cate Memory GM
WriteData
Extend
Zero
Branch Jump
- PCSrc
ResultSrc MornWrite ALUSrc ImmSrc RegWrite
Main Decoder
open
ALUOP+%
funct320 funct7g
ALU Decoder
ALUControl
Figure 0. Single-cycle RISC-V datapath and control unit
For the instruction beq sl, s2, Label, which of the datapath elements are active and why? In addition, to execute this instruction, what should be the outputs of the control unit? Specify the outputs of the control unit in Table 0 using 0, 1 and X (don't care) signals and for the ALU Unit, the type of operation, e.g. addition, subtraction, etc.
Table 0. Control Unit signals
Signal name PCSrc ResultSrc MemWrite ALUControl ALUSrc ImmSrc RegWrite ALUOp Branch Jump Zero ImmExt
Value
Explain Why

figure 0 shows the datapath and control unit of a single cycle risc v microprocessor pcsrc lnit mernwrite alucoub 1418 tuncls allre ns zer6 rogvrita clk clk a wc3 d rd instruction memory we 79168

Added by Brandon G.

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