For the following problems, unless otherwise stated, assume $\mu_n C_{ox}$=100 $\mu$A/V$^2$, $\mu_p C_{ox}$=200 $\mu$A/V$^2$, $V_{TH}$=0.5 V for
NMSOS and $V_{TH}$=-0.5 V for PMOS devices.
Problem 3. We wish to design the circuit of the figure shown below for a drain current of 1 mA ($I_D$=1mA).
If W/L = 18/0.18, compute $R_1$ and $R_2$ such that the input impedance is at least 20 kΩ.
$V_{DD}$=1.8 V
$R_1$
500 Ω
$M_1$
$R_2$