Question

ECE 271 Homework #3 (Due Wednesday, 17 Feb) 0/1 M 0/0 1/0 1/0 N P 0/0 1/1 The above Mealy FSM receives an infinite sequence of logic 1's and 0's as input. It outputs a logic 1 every time two consecutive logic 1's or two consecutive logic 0's are input. (Convince yourself that is true.) 1) (2 points) Prove the FSM cannot be made with a fewer number of states. 2) (4 points) Give a complete schematic for the FSM. (Use state assignments M = '01', N = '10', P = '11'.) 3) (2 points) Construct a timing diagram for your design from the previous problem. Assume the input sequence is r = '1011010001'. (The most significant bit is input first.) 4) (2 points) Assume the FSM is physically implemented in a PAL16R4. Explain how you would initialize the FSM. (Hint: Consider how you would synchronously initialize the FSM)

          ECE 271 Homework #3 (Due Wednesday, 17 Feb)

0/1
M
0/0
1/0
1/0
N
P
0/0
1/1

The above Mealy FSM receives an infinite sequence of logic 1's and 0's as input. It outputs a
logic 1 every time two consecutive logic 1's or two consecutive logic 0's are input. (Convince
yourself that is true.)

1) (2 points) Prove the FSM cannot be made with a fewer number of states.

2) (4 points) Give a complete schematic for the FSM. (Use state assignments M = '01', N =
'10', P = '11'.)

3) (2 points) Construct a timing diagram for your design from the previous problem. Assume
the input sequence is r = '1011010001'. (The most significant bit is input first.)

4) (2 points) Assume the FSM is physically implemented in a PAL16R4. Explain how you
would initialize the FSM. (Hint: Consider how you would synchronously initialize the
FSM)

ECE 271 Homework #3 (Due Wednesday, 17 Feb)

0/1
M
0/0
1/0
1/0
N
P
0/0
1/1

The above Mealy FSM receives an infinite sequence of logic 1's and 0's as input. It outputs a
logic 1 every time two consecutive logic 1's or two consecutive logic 0's are input. (Convince
yourself that is true.)

1) (2 points) Prove the FSM cannot be made with a fewer number of states.

2) (4 points) Give a complete schematic for the FSM. (Use state assignments M = '01', N =
'10', P = '11'.)

3) (2 points) Construct a timing diagram for your design from the previous problem. Assume
the input sequence is r = '1011010001'. (The most significant bit is input first.)

4) (2 points) Assume the FSM is physically implemented in a PAL16R4. Explain how you
would initialize the FSM. (Hint: Consider how you would synchronously initialize the
FSM)

Added by Marilyn S.

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