Question

Problem 7 (10 points) Suppose we are currently executing the instruction at address 200. XR is index register and R1 is a processor register used for register addressing modes. For the given scenario, fill out the table with effective address and content of AC. Address Memory 100 Load to AC \textbar mode \textbar Address=300 R1 = 200 200 300 XR = 100 300 400 301 190 302 250 400 120 401 110 402 900 Addressing mode Effective address Content of AC Direct address mode Indirect address mode Register indirect mode Relative address mode Indexed address mode Problem 8 (8+5=13 points) a) Assume we have a RISC instruction pipeline with 3-segments I, A, and E as presented in class¹. What kind of pipeline conflict/difficulty is present in the following code? fix the code to solve the problem (as the compiler does) AND draw the space time diagram of the instruction pipeline. LOAD: R1 \leftarrow M [Adr1] LOAD: R2 \leftarrow M [Adr2] ADD: R3 \leftarrow R1 + R2

          Problem 7 (10 points)
Suppose we are currently executing the
instruction at address 200. XR is index
register and R1 is a processor register used
for register addressing modes. For the
given scenario, fill out the table with
effective address and content of AC.
Address	Memory
100	Load to AC \textbar mode \textbar Address=300	R1 = 200
200	300	XR = 100
300	400
301	190
302	250
400	120
401	110
402	900
Addressing mode	Effective address	Content of AC
Direct address mode
Indirect address mode
Register indirect mode
Relative address mode
Indexed address mode
Problem 8 (8+5=13 points)
a) Assume we have a RISC instruction pipeline with 3-segments I, A, and E as presented in class¹. What kind of
pipeline conflict/difficulty is present in the following code? fix the code to solve the problem (as the compiler
does) AND draw the space time diagram of the instruction pipeline.
LOAD: R1 \leftarrow M [Adr1]
LOAD: R2 \leftarrow M [Adr2]
ADD: R3 \leftarrow R1 + R2

Problem 7 (10 points)
Suppose we are currently executing the
instruction at address 200. XR is index
register and R1 is a processor register used
for register addressing modes. For the
given scenario, fill out the table with
effective address and content of AC.
Address Memory
100 Load to AC mode Address=300 R1 = 200
200 300 XR = 100
300 400
301 190
302 250
400 120
401 110
402 900
Addressing mode Effective address Content of AC
Direct address mode
Indirect address mode
Register indirect mode
Relative address mode
Indexed address mode
Problem 8 (8+5=13 points)
a) Assume we have a RISC instruction pipeline with 3-segments I, A, and E as presented in class¹. What kind of
pipeline conflict/difficulty is present in the following code? fix the code to solve the problem (as the compiler
does) AND draw the space time diagram of the instruction pipeline.
LOAD: R1 ←M [Adr1]
LOAD: R2 ←M [Adr2]
ADD: R3 ←R1 + R2

Added by Michael G.

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