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Problem 4 (30 marks) Use the following code fragment: Loop: LD x1,0(x2) ;load x1 from address 0+x2 ADDI x1, x1,1 ;x1=x1+1 SD x1, 0(x2) ; store R1 at address 0+R2 ADDI x2, x2,4 ;x2=x2+4 SUB x4, x3,x2 ;x4=x3-x2 BNEZ x4, Loop ; branch to Loop if x4!=0 Assume that the initial value of x3 is x2 + 396. Further assume that the branch addresses are calculated during the ID phase and branch prediction is handled as designated in the tables 2.1 of the appendix. a. (3 pts) Data hazards are caused by data dependences in the code. List all of the data dependences in the code above. Record the register, source instruction, and destination instruction; for example, there is a data dependency for register R1 from the LW to the ADDI. b. (6 pts) Show the timing of this instruction sequence for the 5-stage RISC pipeline without any forwarding or bypassing hardware but assuming that a register read and a write in the same clock cycle ""forwards"

          Problem 4 (30 marks)
Use the following code fragment:
Loop: LD x1,0(x2) ;load x1 from address 0+x2
ADDI x1, x1,1 ;x1=x1+1
SD x1, 0(x2) ; store R1 at address 0+R2
ADDI x2, x2,4 ;x2=x2+4
SUB x4, x3,x2 ;x4=x3-x2
BNEZ x4, Loop ; branch to Loop if x4!=0
Assume that the initial value of x3 is x2 + 396.
Further assume that the branch addresses are calculated during the ID phase and branch prediction is
handled as designated in the tables 2.1 of the appendix.
a. (3 pts) Data hazards are caused by data dependences in the code. List all of the data dependences in the
code above. Record the register, source instruction, and destination instruction; for example, there is a
data dependency for register R1 from the LW to the ADDI.
b. (6 pts) Show the timing of this instruction sequence for the 5-stage RISC pipeline without any forwarding
or bypassing hardware but assuming that a register read and a write in the same clock cycle ""forwards"

Problem 4 (30 marks)
Use the following code fragment:
Loop: LD x1,0(x2) ;load x1 from address 0+x2
ADDI x1, x1,1 ;x1=x1+1
SD x1, 0(x2) ; store R1 at address 0+R2
ADDI x2, x2,4 ;x2=x2+4
SUB x4, x3,x2 ;x4=x3-x2
BNEZ x4, Loop ; branch to Loop if x4!=0
Assume that the initial value of x3 is x2 + 396.
Further assume that the branch addresses are calculated during the ID phase and branch prediction is
handled as designated in the tables 2.1 of the appendix.
a. (3 pts) Data hazards are caused by data dependences in the code. List all of the data dependences in the
code above. Record the register, source instruction, and destination instruction; for example, there is a
data dependency for register R1 from the LW to the ADDI.
b. (6 pts) Show the timing of this instruction sequence for the 5-stage RISC pipeline without any forwarding
or bypassing hardware but assuming that a register read and a write in the same clock cycle ""forwards"

Added by Trinidad A.

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