Problem 1 [20 pts] Design a Verilog code for '1001' sequence detection module (same design as in

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Problem 1 [20 pts] Design a Verilog code for '1001' sequence detection module (same design as in HW#1-Q3) with various modeling styles: (i) behavioral Verilog description with state table; (ii) a data flow Verilog description with logic equations; and (iii) a structural Verilog description. Submit your codes and test results with waveforms for (i)(ii) and (iii). For the flip-flop, either rising-edge triggering or falling-edge triggering will be OK. X= 00100100110011001 Z= 00000100100010001 Present Next State State X=0 X=1 Present Output X=0 X=1 So So S1 0 0 S1 S2 S1 0 0 S2 S3 S1 0 0 S3 So S1 0 1

          Problem 1 [20 pts] Design a Verilog code for '1001' sequence detection module (same design as in
HW#1-Q3) with various modeling styles: (i) behavioral Verilog description with state table; (ii) a data
flow Verilog description with logic equations; and (iii) a structural Verilog description. Submit your
codes and test results with waveforms for (i)(ii) and (iii). For the flip-flop, either rising-edge triggering or
falling-edge triggering will be OK.
X= 00100100110011001
Z= 00000100100010001
Present
Next State
State
X=0
X=1
Present Output
X=0 X=1
So
So
S1
0
0
S1
S2
S1
0
0
S2
S3
S1
0
0
S3
So
S1
0
1

Problem 1 [20 pts] Design a Verilog code for '1001' sequence detection module (same design as in
HW#1-Q3) with various modeling styles: (i) behavioral Verilog description with state table; (ii) a data
flow Verilog description with logic equations; and (iii) a structural Verilog description. Submit your
codes and test results with waveforms for (i)(ii) and (iii). For the flip-flop, either rising-edge triggering or
falling-edge triggering will be OK.
X= 00100100110011001
Z= 00000100100010001
Present
Next State
State
X=0
X=1
Present Output
X=0 X=1
So
So
S1
0
0
S1
S2
S1
0
0
S2
S3
S1
0
0
S3
So
S1
0
1

Added by Kenneth P.

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