Question

Problem # 1 Assume the following RISC-V assembly code: addi x12, x12, 0 TOP: slli x5, x12, 3 add x6, x10, x5 ld x7, 0(x6) ld x29, 8(x6) sub x30, x7, x29 add x31, x11, x5 sd x30, 0(x31) addi x12, x12, 2 bne x12, x13, TOP Assume the two-issue, statically scheduled processor that has the following properties: • One instruction must be a memory operation; the other must be an arithmetic/logic instruction or a branch. • The processor has all possible forwarding paths between stages (including paths to the ID stage for branch resolution). • The processor has perfect branch prediction. • Two instructions may not issue together in a packet if one depends on the other. • If a stall is necessary, both instructions in the issue packet must stall. 1. Draw an instruction scheduling diagram on how RISC-V code given above executes on the two-issue processor. Assume that the loop exits after one iteration. 2. What is the speedup of going from a one-issue to a two-issue processor? (compare IPC for the two cases).

          Problem # 1
Assume the following RISC-V assembly code:
addi x12, x12, 0
TOP: slli x5, x12, 3
add x6, x10, x5
ld x7, 0(x6)
ld x29, 8(x6)
sub x30, x7, x29
add x31, x11, x5
sd x30, 0(x31)
addi x12, x12, 2
bne x12, x13, TOP
Assume the two-issue, statically scheduled processor that has the following properties:
• One instruction must be a memory operation; the other must be an arithmetic/logic instruction or a branch.
• The processor has all possible forwarding paths between stages (including paths to the ID stage for branch resolution).
• The processor has perfect branch prediction.
• Two instructions may not issue together in a packet if one depends on the other.
• If a stall is necessary, both instructions in the issue packet must stall.
1. Draw an instruction scheduling diagram on how RISC-V code given above executes on the two-issue processor. Assume that the loop exits after one iteration.
2. What is the speedup of going from a one-issue to a two-issue processor? (compare IPC for the two cases).

problem 1 assume the following risc v assembly code addi x12 x12 0 top slli x5 x12 3 add x6 x10 x5 ld x7 0x6 ld x29 8x6 sub x30 x7 x29 add x31 x11 x5 sd x30 0x31 addi x12 x12 2 bne x12 x13 t 95029

Added by Phillip R.

Question

Please give Ace some feedback