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Problem #2 (30 points) Suppose the DLX architecture is modified so that each instruction's execution takes 7 clock cycles (execute phase is Ex1, EX2), MEM phase for data memory takes two cycles M1,M2 i.e., ALU is not internally pipelined, and also memory is not internally pipelined i.e., there can be one instruction using the ALU or the memory: IF ID EX1 EX2 MEM1 MEM2 WB. Repeat problem 1 with the above 7 stage pipeline. Indicate the comparators needed to detect the stall if one exists and the comparators needed for forwarding as well. 1) ADD R7, R4, R3 LW R8, R7(40) MUL R6, R7, R5 LW R2, R8(40) SUB R6, R4, R2 2) SUB R7, R3, R4 LW R8, R7(40) SW R7(40), R8 ADD R3, R5, R7 LW R5, R3(30) 3) ADDI R4, R3, #5 SUB R8, R3, R5 SW R8(40), R7 ADD R3, R5, R8 LW R5, R3(30)

          Problem #2 (30 points) Suppose the DLX architecture is modified so that each
instruction's execution takes 7 clock cycles (execute phase is Ex1, EX2), MEM phase for
data memory takes two cycles M1,M2 i.e., ALU is not internally pipelined, and also
memory is not internally pipelined i.e., there can be one instruction using the ALU or the
memory:
IF ID EX1 EX2 MEM1 MEM2 WB.
Repeat problem 1 with the above 7 stage pipeline. Indicate the comparators needed to
detect the stall if one exists and the comparators needed for forwarding as well.
1) ADD R7, R4, R3
LW R8, R7(40)
MUL R6, R7, R5
LW R2, R8(40)
SUB R6, R4, R2
2) SUB R7, R3, R4
LW R8, R7(40)
SW R7(40), R8
ADD R3, R5, R7
LW R5, R3(30)
3) ADDI R4, R3, #5
SUB R8, R3, R5
SW R8(40), R7
ADD R3, R5, R8
LW R5, R3(30)

Problem #2 (30 points) Suppose the DLX architecture is modified so that each
instruction's execution takes 7 clock cycles (execute phase is Ex1, EX2), MEM phase for
data memory takes two cycles M1,M2 i.e., ALU is not internally pipelined, and also
memory is not internally pipelined i.e., there can be one instruction using the ALU or the
memory:
IF ID EX1 EX2 MEM1 MEM2 WB.
Repeat problem 1 with the above 7 stage pipeline. Indicate the comparators needed to
detect the stall if one exists and the comparators needed for forwarding as well.
1) ADD R7, R4, R3
LW R8, R7(40)
MUL R6, R7, R5
LW R2, R8(40)
SUB R6, R4, R2
2) SUB R7, R3, R4
LW R8, R7(40)
SW R7(40), R8
ADD R3, R5, R7
LW R5, R3(30)
3) ADDI R4, R3, #5
SUB R8, R3, R5
SW R8(40), R7
ADD R3, R5, R8
LW R5, R3(30)

Added by Cassandra H.

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