Question

Problem 4. Ser in Shift_load CLK Write the complete hierarchical VHDL code for the four-bit shift register shown above. Use the signal names shown. When shift_load is 1, parallel data is loaded. When shift_load is 0, data is shifted from left to right, i.e., serial data is shifted into the most significant bit. a. Write the complete behavioral code for one stage of the shift register. [10] Prob. 4 (cont) b. Write the complete hierarchical code for the four-bit shift register by creating a component for one stage of the register and connecting the four stages using PORT MAP statements. [15]

          Problem 4.
Ser in
Shift_load
CLK
Write the complete hierarchical VHDL code for the four-bit shift register shown above. Use the signal names
shown. When shift_load is 1, parallel data is loaded. When shift_load is 0, data is shifted from left to right, i.e.,
serial data is shifted into the most significant bit.
a.
Write the complete behavioral code for one stage of the shift register.
[10]
Prob. 4 (cont)
b.
Write the complete hierarchical code for the four-bit shift register by creating a component for one stage of the
register and connecting the four stages using PORT MAP statements.
[15]

Problem 4.
Ser in
Shiftload
CLK
Write the complete hierarchical VHDL code for the four-bit shift register shown above. Use the signal names
shown. When shiftload is 1, parallel data is loaded. When shiftload is 0, data is shifted from left to right, i.e.,
serial data is shifted into the most significant bit.
a.
Write the complete behavioral code for one stage of the shift register.
[10]
Prob. 4 (cont)
b.
Write the complete hierarchical code for the four-bit shift register by creating a component for one stage of the
register and connecting the four stages using PORT MAP statements.
[15]

Added by Rachel F.

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