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Problem #4 (Priority Encoder) [15 points] We want to design a high priority encoder that provides as an output the signals corresponding to the highest TWO input signals. The circuit has 8 active low request signals (I0, I1, ..., I7) and 8 active high outputs: (A0, A1, A2) which indicate the value of the highest input request, (B0, B1, B2) which indicate the value of the second highest input request, (AVALID) which is activated if at least one input signal is active, and (BVALID) which is activated to reflect that there is a second input request activated. You can use all types of gates and as building blocks, you can use encoders and decoders. Problem #5 (Priority Encoder) [15 points] Implement the circuit of problem #4 using VHDL and write a testbench to verify its functionality. Provide printouts of your code including test bench file in addition to snapshots of the obtained simulation waveforms.

          Problem #4 (Priority Encoder) [15 points] We want to design a high priority encoder that provides as an output the signals corresponding to the highest TWO input signals. The circuit has 8 active low request signals (I0, I1, ..., I7) and 8 active high outputs: (A0, A1, A2) which indicate the value of the highest input request, (B0, B1, B2) which indicate the value of the second highest input request, (AVALID) which is activated if at least one input signal is active, and (BVALID) which is activated to reflect that there is a second input request activated. You can use all types of gates and as building blocks, you can use encoders and decoders. Problem #5 (Priority Encoder) [15 points] Implement the circuit of problem #4 using VHDL and write a testbench to verify its functionality. Provide printouts of your code including test bench file in addition to snapshots of the obtained simulation waveforms.

Problem #4 (Priority Encoder) [15 points] We want to design a high priority encoder that provides as an output the signals corresponding to the highest TWO input signals. The circuit has 8 active low request signals (I0, I1, ..., I7) and 8 active high outputs: (A0, A1, A2) which indicate the value of the highest input request, (B0, B1, B2) which indicate the value of the second highest input request, (AVALID) which is activated if at least one input signal is active, and (BVALID) which is activated to reflect that there is a second input request activated. You can use all types of gates and as building blocks, you can use encoders and decoders. Problem #5 (Priority Encoder) [15 points] Implement the circuit of problem #4 using VHDL and write a testbench to verify its functionality. Provide printouts of your code including test bench file in addition to snapshots of the obtained simulation waveforms.

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