Question

Q-10: Let input of registers inside are D and output are Q. Write modules using two methods of port connections.

          Q-10: Let input of registers inside are D and output are Q.
Write modules using two methods of port connections.

Added by Rodrigo M.

Computer Science and Information Technology

Trishna Knowledge Systems 2018 Edition

Instant Answer

Solved by Expert Manish Jain

01/09/2022

Step 1

Step 1: **Method 1: Using individual ports** ```verilog module shift_reg ( input clk, input [3:0] reg_in, output [3:0] reg_out ); reg [3:0] reg_data; always @(posedge clk) begin reg_data <= reg_in; end assign reg_out = reg_data; endmodule ``` Show more…

Show all steps

Thanks for your feedback!

Q-10: Let input of registers inside are D and output are Q. Write modules using two methods of port connections. reg\_in [3:0] shift\_reg reg\_out [3:0] clock (4 bit)