00:01
Hi to everyone, so for a1 to implement the lwi, lwi rt, rd rs, interpretation reg, rt, mem, reg, rd plus reg, rs.
00:31
So to implement this we can use the following exchange alu for the additional operation.
00:46
Agd, rg, alu, mux for selecting output of alu, dmem to access memory using calculated address, regs to store result in reg, rt.
01:19
B is false, false, new function, new functional block are not needed for this instruction.
01:45
So you can use the existing block mentioned in part 1.
01:50
So one problem, so here a, a, if only things we need to do is to face the consecutive instruction.
02:11
So cycle time equals latency of i mem, so 200 ps...