Question

Question 25 Below is the sequence of 12 memory address references given as word addresses: 0,1,9,4,1,17,9,7,0,9,12,4 Assume a cache is 2-way set associative with LRU replacement policy, uses 1-word blocks, and has a total size of 16 blocks. Then for each of the addresses in the sequence, please indicate if it will be a miss or a hit in this cache (initially empty). If it is a miss, also show its miss type.

          Question 25
Below is the sequence of 12 memory address references given as word addresses:
0,1,9,4,1,17,9,7,0,9,12,4
Assume a cache is 2-way set associative with LRU replacement policy, uses 1-word blocks, and has a total size of 16 blocks. Then for each of the addresses in the sequence, please indicate if it will be a miss or a hit in this cache (initially empty). If it is a miss, also show its miss type.

Question 25
Below is the sequence of 12 memory address references given as word addresses:
0,1,9,4,1,17,9,7,0,9,12,4
Assume a cache is 2-way set associative with LRU replacement policy, uses 1-word blocks, and has a total size of 16 blocks. Then for each of the addresses in the sequence, please indicate if it will be a miss or a hit in this cache (initially empty). If it is a miss, also show its miss type.

Added by Lourdes B.

Computer Science and Information Technology

Trishna Knowledge Systems 2018 Edition

Instant Answer

Solved by Expert Akash M

12/11/2023

Step 1

Since the cache is 2-way set associative and has a total size of 16 blocks, each set will have 8 blocks (16 blocks / 2 sets = 8 blocks per set). Now, let's go through the sequence of memory address references and determine if each address will be a miss or a hit Show more…

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Questions & Answers (8 points each * 4): Question 25 Below is the sequence of 12 memory address references given as word addresses: 0,1,9,4,1,17,9,7,0,9,12,4 Assume a cache is 2-way set associative with LRU replacement policy, uses 1-word blocks, and has a total size of 16 blocks. Then for each of the addresses in the sequence, please indicate if it will be a miss or a hit in this cache (initially empty). If it is a miss, also show its miss type.