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Problem 2: Use Design Compiler (DC) to generate a timing report for the following circuit by listing the critical path and false path by cell name in your schematics. Circuit C1: Figl. Circuit CI. Cell name Logic gate type Delay B_1, B_2 buffer 10 ps B_0,B_3 buffer 80 ps I_0 inverter 10 ps m1,m2 2-to-1 MUX use cell library value Tablel. Delay Specification of C1 Instructions: 1) Write a synthesizable structural model with SV, do not apply any delay in your SV code. 2) Synthesize your SV model with DC. ? As DC optimizes the design, you should use "Compile -no_map -only_design_rule" to compile your design. ? After the successful compilation, use "write_sdf" to generate your cell delay spec file (.sdf file). ? Find the buffer and inverter in your .sdf file and modify the delay values to the required values in the table. 3) Use "read_sdf" to read the modified delay spec file. 4) Use DC to find the critical path and false path (if any). 5) Generate the timing report by "report_timing", save it in a text named "your design name.txt".

          Problem 2: Use Design Compiler (DC) to generate a timing report for the following circuit by listing the
critical path and false path by cell name in your schematics.
Circuit C1:
Figl. Circuit CI.
Cell name	Logic gate type	Delay
B_1, B_2	buffer	10 ps
B_0,B_3	buffer	80 ps
I_0	inverter	10 ps
m1,m2	2-to-1 MUX	use cell library value
Tablel. Delay Specification of C1
Instructions:
1) Write a synthesizable structural model with SV, do not apply any delay in your SV code.
2) Synthesize your SV model with DC.
? As DC optimizes the design, you should use "Compile -no_map -only_design_rule" to compile
your design.
? After the successful compilation, use "write_sdf" to generate your cell delay spec file (.sdf file).
? Find the buffer and inverter in your .sdf file and modify the delay values to the required values in
the table.
3) Use "read_sdf" to read the modified delay spec file.
4) Use DC to find the critical path and false path (if any).
5) Generate the timing report by "report_timing", save it in a text named "your design name.txt".

Problem 2: Use Design Compiler (DC) to generate a timing report for the following circuit by listing the
critical path and false path by cell name in your schematics.
Circuit C1:
Figl. Circuit CI.
Cell name Logic gate type Delay
B1, B2 buffer 10 ps
B0,B3 buffer 80 ps
I0 inverter 10 ps
m1,m2 2-to-1 MUX use cell library value
Tablel. Delay Specification of C1
Instructions:
1) Write a synthesizable structural model with SV, do not apply any delay in your SV code.
2) Synthesize your SV model with DC.
? As DC optimizes the design, you should use "Compile -nomap -onlydesignrule" to compile
your design.
? After the successful compilation, use "writesdf" to generate your cell delay spec file (.sdf file).
? Find the buffer and inverter in your .sdf file and modify the delay values to the required values in
the table.
3) Use "readsdf" to read the modified delay spec file.
4) Use DC to find the critical path and false path (if any).
5) Generate the timing report by "reporttiming", save it in a text named "your design name.txt".

Added by Matthew S.

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