The figure below shows the state transition diagram of a finite state machine (FSM) that is designed for
the purpose of detection of two unique sequences of codes and the entity diagram for its intended
operation.
The outputs of the FSM are defined in the following table:
Input A is a synchronous single-bit data input. State transitions may occur at every rising clock edge on
the synchronizing clock input clk. A bit stream should be applied on input A and based on the state of
B, the FSM can detect either the sequential code " 1001 " when B=^(')0 ' or the code " 1011 " when B=^(')1 '.
The figure below shows the state transition diagram of a finite state machine (FSM) that is designed for the purpose of detection of two unique sequences of codes and the entity diagram for its intended operation. A'
AB'
3 />current
A
A'
Reset
B
>detection
A
A'B
S1
so
S2
FSM
reset-
A'B'
AB
A
A
S3
A
A
clk
A'
S4
A
The outputs of the FSM are defined in the following table:
States Outputs
so
s1
S2
S3
S4
S5
current
000
001
010
011
100
101
detection
0
0
0
0
0
1 Input A is a synchronous single-bit data input. State transitions may occur at every rising clock edge on the synchronizing clock input clk. A bit stream should be applied on input A and based on the state of B, the FSM can detect either the sequential code "1001 when B=0' or the code "1011 when B=1'.