Question

FSM: 3*i - 2 Sequence A FSM with 4 state bits can generate the the sequence: 1,4,7,10,13. Complete the following Verilog using only AND, OR and NOT gates for the next_pattern module. The dff module also has to be completed. A manual check for gates will be performed later. Editor // pos edge d flip-flop with init module dff #(parameter N=4, init=0) ( output logic [N-1:0] q, input logic [N-1:0] d, input logic clk, reset ); always_ff @(posedge clk) q <= reset ? init : d; endmodule module next_pattern(output logic [3:0] next, input logic [3:0] cur); // complete next pattern for sequence: // 1, 4, 7, 10, 13 endmodule module fsm #(parameter init=1) ( output logic [3:0] cur, input logic clock, reset ); logic [3:0] next; next_pattern next_fn( next, cur ); dff #(4, init) state( cur, next, clock, reset); endmodule

          FSM: 3*i - 2 Sequence
A FSM with 4 state bits can generate the the sequence: 1,4,7,10,13. Complete the following Verilog using only AND, OR and NOT gates for the next_pattern module. The dff module also has to be completed. A manual check for gates will be performed later.

Editor
// pos edge d flip-flop with init
module dff #(parameter N=4, init=0) (
output logic [N-1:0] q, input logic [N-1:0] d,
input logic clk, reset );
always_ff @(posedge clk) q <= reset ? init : d;
endmodule

module next_pattern(output logic [3:0] next, input logic [3:0] cur);
// complete next pattern for sequence:
// 1, 4, 7, 10, 13
endmodule

module fsm #(parameter init=1) (
output logic [3:0] cur, input logic clock, reset );
logic [3:0] next;
next_pattern next_fn( next, cur );
dff #(4, init) state( cur, next, clock, reset);
endmodule

FSM: 3*i - 2 Sequence
A FSM with 4 state bits can generate the the sequence: 1,4,7,10,13. Complete the following Verilog using only AND, OR and NOT gates for the nextpattern module. The dff module also has to be completed. A manual check for gates will be performed later.

Editor
// pos edge d flip-flop with init
module dff #(parameter N=4, init=0) (
output logic [N-1:0] q, input logic [N-1:0] d,
input logic clk, reset );
alwaysff @(posedge clk) q <= reset ? init : d;
endmodule

module nextpattern(output logic [3:0] next, input logic [3:0] cur);
// complete next pattern for sequence:
// 1, 4, 7, 10, 13
endmodule

module fsm #(parameter init=1) (
output logic [3:0] cur, input logic clock, reset );
logic [3:0] next;
nextpattern nextfn( next, cur );
dff #(4, init) state( cur, next, clock, reset);
endmodule

Added by Tanya P.

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