2. Design a Mealy FSM that will detect the sequence "1001" with overlap (i.e. the bit stream "1001001" will be detected as two instances of the sequence). Input is a 1-bit signal named A. The output, Y, should be a '1' when a sequence has been detected and '0' otherwise. Use D flip-flops for state memory and set the next-state and outputs of unused states to the Reset state and '0', respectively. Show the state transition diagram, state assignment table, state transition table, next-state equations, and output equations. Use K-maps to extract the most simplified equations. (35 pts) 3. Design a Moore FSM for the problem above. (30 pts)
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The state diagram of a sequence detector which allows overlap is shown below. The sequence detector accepts as input a string of bits. Its output goes high when the target sequence has been detected. In a sequence detector that allows overlap, the final bits of one sequence can be the start of another sequence. Using the state diagram given below and an input sequence 10110, assign binary values to the states and derive the state table. Then, derive the simplified state equations using JK flip-flops and design a synchronous sequence detector circuit. Is this a Mealy or Moore model? Treat unused states as don't care conditions.
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