Using Logisim, implement the next algorithm to simulate the hardware circuit of the unsigned multiplication algorithm studied in the slides (8-bit).
Use Logisim to simulate the hardware circuit of the signed multiplication algorithm studied in the slides for an 8-bit multiplier and multiplicand.
Unsigned Sequential Multiplier:
* Initialize: HI = 0
Start
* Initialize: LO = Multiplier
HI = 0, LO = Multiplier
Final Product in HI and LO registers
* Repeat for each bit of Multiplier
LO[0]
Multiplicand 32 bits
32 bits
Carry.Sum = HI + Multiplicand
32-bit ALU
add
HI, LO = Shift Right (Carry, Sum, LO)
Sum
32 bits
32nd Repetition? Yes Done
No
shift right Control write
HI LO 64 bits
LO[0]
Signed Sequential Multiplier:
ALU produces: 32-bit sum + sign bit
Start
* Sign bit can be computed:
HI = 0, LO = Multiplier
No overflow: sign = sum[31]
If Overflow: sign = ~sum[31]
LO[0]?
Multiplicand 32 bits
31 iterations
Sign, Sum = HI + Multiplicand
Last iteration
Sign, Sum = HI - Multiplicand
32-bit
32-bit ALU
qns 'ppe
HI, LO = Shift Right (Sign, Sum, LO)
sign
sum 32 bits
No
shift right Control write
32nd Repetition?
HI
LO
Yes Done
64 bits
LO[0]