6. In signed value addition, by checking the sign of inputs and output, we can recognize whether overflow has occurred or not. When we have the following Arithmetic/Logic Unit (ALU) providing 32-bit output with two 32-bit inputs. Design a logic circuit for an overflow indicator in signed value addition. The signal for enabling addition is EN_ADD. When EN_ADD=1, addition operation is activated. (The EN_ADD signal is set to 1 when signed value addition 'ADD' in assembly language is translated to machine language.) We are using 2's complement to represent the integer values, i.e., inputs and outputs. ALU (Arithmetic/Logic Unit) 32-bit (Input1) a31 - a0 32-bit v31 - v0 (Output) 32-bit (Input2) b31 - b0 EN_ADD The output signal of the logic circuit, denoted by 'F' is just one bit signal, and F=0 and F=1 represent non-overflow and overflow respectively. Show your work for designing a logic circuit to indicate overflow in signed value addition. You need to determine inputs of this circuit. Inputs? Overflow indicator digital logic circuit F
Added by Christopher B.
Close
Step 1
Overflow occurs if: - Adding two positive numbers results in a negative number. - Adding two negative numbers results in a positive number. Show more…
Show all steps
Your feedback will help us improve your experience
Akash M and 87 other AP CS educators are ready to help you.
Ask a new question
Labs
Want to see this concept in action?
Explore this concept interactively to see how it behaves as you change inputs.
Key Concepts
Recommended Videos
Adi S.
Design a combinational circuit for a new brand of computers that will take a 4-bit binary number as input and output 1 if the input contains at least 2 zeros. For example: i) Input 0000: output 1 (4 zeros) ii) Input 0001: output 1 (3 zeros) iii) Input 0011: output 1 (2 zeros) iv) Input 0111: output 0 (1 zero) b) Draw the minimum cost AND-OR implementation for the function below. Input variables are available in true and complement forms. F(A,B,C,D)= ÎŁm(1,3,6,7,11,14,15)+D(5,9,10) c) An electronic gate has a digital logic circuit whose output is a "1" if majority of the input variables are 1's. The output is a zero (0) otherwise. Using a truth table find the Boolean function implemented by a three (3) input variable majority gate Design the electronic gate a) Design a combinatorial circuit that will be able to detect prime numbers given as input in binary. The input to the system will be any 4 bit binary number. The output of the circuit should be a single bit that will be 1 (high) if the input is a prime number and 0 (low) if the input is not a prime number. For example, if the input to the circuit is 0101 the output should be 1. Again if the input is 1010, the output should be 0. b) Implement the function below together with the don't care condition given below using only two NOR gates. Assume that both the normal and complement inputs are available. F(A,B,C,D) = ÎŁm (1, 3, 5, 6) d(A,B,C,D) = ÎŁm (8, 10, 14, 15) c) Design a function that will take a 3 bit binary number as input and the output will be "HIGH" if total number of 1s in input is less than or equal to total number of 0s and "LOW" otherwise.
Sri K.
(c) Design a 4-bit even parity generator, which has four-bit binary inputs (A3, A2, A1, A0) and produces one output; P. The output P is HIGH (1) if the number of 1's in the input vector are odd. Output P is LOW if the number of 1's in the input vector are even. Implement this parity generator using multiplexer IC 74LS138 (8-to-1 multiplexer) as shown in Figure Q2(c). Show all the steps and wiring of the IC 74LS138. Vcc So S1 S2 EN GND
Stanley E.
Recommended Textbooks
Computer Science and Information Technology
Introduction to Programming Using Python
Computer Science - An Overview
Transcript
Watch the video solution with this free unlock.
EMAIL
PASSWORD