Question

a) Using minimum number of D-Flip Flops and other needed components, show the design of a 3-bit register Q that has two control inputs: Load and Shift. The register has a 3-bit external input I2I1I0 and a serial input Sin. The table below shows the functionality of the register: Load | Shift | Action 0 | 0 | No change in Q 1 | X | Load parallel input (i.e. I2I1I0 -> Q2Q1Q0) 0 | 1 | Shift Q to the right with Sin inserted from the left (i.e., most significant bit) b) Complete the following table by showing the content of register Q after each clock cycle: Clock # | Load | Shift | Sin | D2 D1 D0 | Q2 Q1 Q0 1 | 0 | 0 | 0 | 0 0 0 | 0 0 0 2 | 1 | 0 | 0 | 1 0 1 | 0 0 0 3 | 0 | 1 | 1 | 1 1 1 | 1 0 1 4 | 0 | 0 | 1 | 0 0 1 | 5 | 0 | 1 | 0 | 0 0 0 | 6 | 1 | 1 | 0 | 1 0 0 | 7 | 0 | 0 | 1 | 1 1 0 | Remember that inputs in a cycle affect the register in the next cycle.

          a) Using minimum number of D-Flip Flops and other needed components, show the design of a 3-bit register Q that has two control inputs: Load and Shift. The register has a 3-bit external input I2I1I0 and a serial input Sin. The table below shows the functionality of the register:

Load | Shift | Action
0 | 0 | No change in Q
1 | X | Load parallel input (i.e. I2I1I0 -> Q2Q1Q0)
0 | 1 | Shift Q to the right with Sin inserted from the left (i.e., most significant bit)

b) Complete the following table by showing the content of register Q after each clock cycle:

Clock # | Load | Shift | Sin | D2 D1 D0 | Q2 Q1 Q0
1 | 0 | 0 | 0 | 0 0 0 | 0 0 0
2 | 1 | 0 | 0 | 1 0 1 | 0 0 0
3 | 0 | 1 | 1 | 1 1 1 | 1 0 1
4 | 0 | 0 | 1 | 0 0 1 |
5 | 0 | 1 | 0 | 0 0 0 |
6 | 1 | 1 | 0 | 1 0 0 |
7 | 0 | 0 | 1 | 1 1 0 |

Remember that inputs in a cycle affect the register in the next cycle.

a) Using minimum number of D-Flip Flops and other needed components, show the design of a 3-bit register Q that has two control inputs: Load and Shift. The register has a 3-bit external input I2I1I0 and a serial input Sin. The table below shows the functionality of the register:

Load | Shift | Action
0 | 0 | No change in Q
1 | X | Load parallel input (i.e. I2I1I0 -> Q2Q1Q0)
0 | 1 | Shift Q to the right with Sin inserted from the left (i.e., most significant bit)

b) Complete the following table by showing the content of register Q after each clock cycle:

Clock # | Load | Shift | Sin | D2 D1 D0 | Q2 Q1 Q0
1 | 0 | 0 | 0 | 0 0 0 | 0 0 0
2 | 1 | 0 | 0 | 1 0 1 | 0 0 0
3 | 0 | 1 | 1 | 1 1 1 | 1 0 1
4 | 0 | 0 | 1 | 0 0 1 |
5 | 0 | 1 | 0 | 0 0 0 |
6 | 1 | 1 | 0 | 1 0 0 |
7 | 0 | 0 | 1 | 1 1 0 |

Remember that inputs in a cycle affect the register in the next cycle.

Added by Lacey M.

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